D12320VF25V Datasheet, PDF (318/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
8.11.2 Register Configuration
Table 8.19 shows the port F register configuration.
Table 8.19 Port F Registers
Name
Abbreviation
R/W
Port F data direction register
PFDDR
W
Port F data register
PFDR
R/W
Port F register
PORTF
R
Bus control register L
BCRL
R/W
System control register
SYSCR
R/W
Port function control register 1 PFCR1
R/W
Port function control register 2 PFCR2
R/W
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Initial Value
H'80/H'00^*2
H'00
Undefined
H'3C
H'01
H'0F
H'30
Address^*1
H'FEBE
H'FF6E
H'FF5E
H'FED5
H'FF39
H'FF45
H'FFAC
Port F Data Direction Register (PFDDR)
Bit
:7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6^*
Initial value : 1
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
Mode 7^*
Initial value : 0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6*, and to
H'00 in mode 7*. It retains its prior state in software standby mode. The OPE bit in SBYCR is
used to select whether the bus control output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 284 of 1108
REJ09B0089-0700