D12320VF25V Datasheet, PDF (828/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 Clock Pulse Generator
18.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 18.1 shows the register configuration.
Table 18.1 Clock Pulse Generator Register
Name
Abbreviation R/W
System clock control register
SCKCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
Address^*
H'FF3A
18.2 Register Descriptions
18.2.1 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
PSTOP —
DIV
—
Initial value :
0
0
0
0
R/W
: R/W
R/W
R/W
—
3
2
1
0
—
SCK2 SCK1 SCK0
0
0
0
0
—
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Normal Operation
φ output (Initial value)
Fixed high
Description
Sleep Mode
Software
Standby Mode
φ output
Fixed high
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Rev.7.00 Feb. 14, 2007 page 794 of 1108
REJ09B0089-0700