D12320VF25V Datasheet, PDF (722/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.22.2 Overview
(1) Block Diagram
Internal address bus
Internal data bus (16 bits)
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
RAMER
Control unit
Memory MAT unit
User MAT: 512 kbytes
User boot MAT: 8 kbytes
Flash memory
Mode pin
Operating
mode
Legend:
FCCS: Flash code control and status register
FPCS: Flash program code select register
FECS: Flash erase code select register
FKEY: Flash key code register
FMATS: Flash MAT select register
FTDAR: Flash transfer destination address register
RAMER: RAM emulation register
Note: To read from or write to any of the registers above except RAMER, the FLSHE bit
in system control register 2 (SYSCR2) must be set to 1.
Figure 17.60 Block Diagram of Flash Memory
Rev.7.00 Feb. 14, 2007 page 688 of 1108
REJ09B0089-0700