D12320VF25V Datasheet, PDF (1062/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SSR1—Serial Status Register 1
H'FF84
Smart Card Interface 1
Bit
:
Initial value :
Read/Write :
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received^*
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Note: * Retains its previous state when the RE bit in SCR is
cleared to 0 with a multiprocessor format.
Transmit End
0 Transmission in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 Transmission has ended
[Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Parity Error
0
[Clearing condition]
When 0 is written to PER after reading PER = 1^*1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR^*2
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception
cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled.
Error Signal Status*
0 Data has been received normally, and there is no error signal
[Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS =1
1 Error signal indicating detection of parity error has been sent by receiving device
[Setting condition]
When the error signal is sampled at the low level
Note: * Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Overrun Error
0
[Clearing condition]
When 0 is written to
ORER
after
reading
ORER
=
1^*1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1^*2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception
cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled.
Receive Data Register Full^*
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: * RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit
in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Note: * Can only be written with 0 for flag clearing.
Rev.7.00 Feb. 14, 2007 page 1028 of 1108
REJ09B0089-0700