D12320VF25V Datasheet, PDF (319/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
Port F Data Register (PFDR)
Bit
:7
PF7DR
Initial value : 0
R/W
: R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port F Register (PORTF)
Bit
:7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Initial value : —^*
—^*
—^*
—^*
—^*
—^*
—^*
—^*
R/W
:R
R
R
R
R
R
R
R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
Port Function Control Register 1 (PFCR1)
Bit
:
Initial value :
R/W
:
7
CSS17
0
R/W
6
5
4
CSS36 PF1CS5S PF0CS4S
0
0
0
R/W
R/W
R/W
3
A23E
1
R/W
2
A22E
1
R/W
1
A21E
1
R/W
0
A20E
1
R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Rev.7.00 Feb. 14, 2007 page 285 of 1108
REJ09B0089-0700