D12320VF25V Datasheet, PDF (846/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Power-Down Modes
19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the
oscillation stabilization time).
Table 19.4 shows the standby times for different operating frequencies and settings of bits STS2 to
STS0.
Table 19.4 Oscillation Stabilization Time Settings
25 20 16 12 10 8 6 4 2
STS2 STS1 STS0 Standby Time MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit
0 0 0 8192 states 0.32 0.41 0.51 0.68 0.8 1.0 1.3 2.0 4.1 ms
1 16384 states 0.65 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2
1 0 32768 states 1.3 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4
1 65536 states 2.6 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8
1 0 0 131072 states 5.2 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5
1 262144 states 10.4 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2
1 0 Reserved
— — ——————— —
1 16 states
0.6 0.8 1.0 1.3 1.6 2.0 2.7 4.0 8.0 μs
: Recommended time setting
Using an External Clock: Any value can be set. Normally, use of the minimum time is
recommended*.
Note: * The 16-state standby time cannot be used in the F-ZTAT versions; a standby time of 8192
states or longer should be used.
19.6.4 Software Standby Mode Application Example
Figure 19.2 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Rev.7.00 Feb. 14, 2007 page 812 of 1108
REJ09B0089-0700