D12320VF25V Datasheet, PDF (243/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
Table 7.10 Number of States Required for Each Execution Phase
Access To:
Bus width
Access states
Execution Vector read
SI
phase
Register
SJ
information
read/write
Byte data read SK
Word data read SK
Byte data write SL
Word data write SL
Internal operation SM
On- On-
Chip Chip Internal I/O
RAM ROM Registers
32 16 8
16
1
1
2
2
—1
——
1
———
1
1
2
2
1
1
4
2
1
1
2
2
1
1
4
2
1
1
1
1
External Devices
8
8
16
2
3
2
4
6+2m 2
———
2
3+m 2
4
6+2m 2
2
3+m 2
4
6+2m 2
1
1
1
16
3
3+m
—
3+m
3+m
3+m
3+m
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev.7.00 Feb. 14, 2007 page 209 of 1108
REJ09B0089-0700