D12320VF25V Datasheet, PDF (600/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.1.2 Register Configuration
The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROM-
related registers are shown in table 17.1.
Table 17.1 ROM Registers
Register Name
Abbreviation R/W
Mode control register
MDCR
R/W
Bus controller register
BCRL
R/W
Note: * Lower 16 bits of the address.
Initial Value
Undefined
Undefined
Address^*
H'FF3B
H'FED5
17.2 Register Descriptions
17.2.1 Mode Control Register (MDCR)
Bit
:
7
6
5
4
—
—
—
—
Initial value :
1
0
0
0
R/W
:—
—
—
—
Note: * Determined by pins MD2 to MD0.
3
2
1
0
—
MDS2 MDS1 MDS0
0
—^*
—^*
—^*
—
R
R
R
MDCR is an 8-bit read-only register used to monitor the current operating mode of the chip.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to
MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0)
input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.
Rev.7.00 Feb. 14, 2007 page 566 of 1108
REJ09B0089-0700