D12320VF25V Datasheet, PDF (732/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the error occurrence during programming or erasing
flash memory and the download of on-chip program.
Bit
:
7
6
5
4
3
2
1
0
—
—
—
FLER
—
—
—
SCO
Initial value :
1
0
0
0
0
0
0
0
R/W
:R
R
R
R
R
R
R
(R)/W
Bit 7—Reserved: This bit is always read as 1. The write value should always be 1.
Bits 6 and 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—Flash Memory Error (FLER): Indicates an error occurs during programming and erasing
flash memory.
When FLER is set to 1, flash memory enters the error protection state.
This bit is initialized at a power-on reset or in hardware standby mode.
When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the
damage to flash memory, the reset must be released after the reset period of 100 μs which is
longer than normal.
Bit 4
FLER
0
1
Description
Flash memory operates normally
(Initial value)
Programming/erasing protection for flash memory (error protection) is invalid.
[Clearing condition] At a power-on reset or in hardware standby mode
Indicates an error occurs during programming/erasing flash memory.
Programming/erasing protection for flash memory (error protection) is valid.
[Setting condition] See section 17.25.3, Error Protection.
Bits 3 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.7.00 Feb. 14, 2007 page 698 of 1108
REJ09B0089-0700