D12320VF25V Datasheet, PDF (168/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.5 Usage Notes
5.5.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared.
Figure 5.8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0.
TIER0 write cycle by CPU
TGI0A exception handling
φ
Internal
address bus
TIER0 address
Internal
write signal
TGIEA
TGFA
TGI0A
interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
Rev.7.00 Feb. 14, 2007 page 134 of 1108
REJ09B0089-0700