D12320VF25V Datasheet, PDF (638/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
• When a bus master other than the CPU (the DTC) has control of the bus during
programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 17.17 shows the flash memory state transition diagram.
Normal operating mode
Program mode
Erase mode
RES = 0 or STBY = 0
Reset or hardware standby
(hardware protection)
RD VF PR ER
FLER = 0
Error
occurrence
Error occurrence
(software standby)
RD VF PR ER
RES = 0 or
FLER = 0
STBY = 0
FLMCR1, FLMCR2,
RES = 0 or
STBY = 0
EBR1, EBR2
initialization state
Error protection mode
Software
standby mode
Error protection mode
(software standby)
RD VF PR ER
FLER = 1
Software standby
mode release
RD VF PR ER
FLER = 1
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 17.17 Flash Memory State Transitions
Rev.7.00 Feb. 14, 2007 page 604 of 1108
REJ09B0089-0700