D12320VF25V Datasheet, PDF (147/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)
Bit
:
7
6
5
4
3
—
IPR6 IPR5 IPR4
—
Initial value :
0
1
1
1
0
R/W
:—
R/W
R/W
R/W
—
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: Read-only bits, always read as 0.
Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
Note: * Reserved bits.
6 to 4
IRQ0
IRQ2
IRQ3
IRQ6
IRQ7
Watchdog timer
—^*
TPU channel 0
TPU channel 2
TPU channel 4
8-bit timer channel 0
—^*
SCI channel 1
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
—^*
A/D converter
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1
SCI channel 0
—^*
Rev.7.00 Feb. 14, 2007 page 113 of 1108
REJ09B0089-0700