D12320VF25V Datasheet, PDF (1023/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

BCRL—Bus Control Register L
Appendix B Internal I/O Registers
H'FED5
Bus Controller
Bit
:
7
6
5
4
3
2
1
0
BRLE BREQOE EAE
⎯
⎯
⎯
⎯ WAITE
Initial value :
0
0
1
1
1
1
0
0
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W
WAIT Pin Enable
0 Wait input by WAIT pin
disabled
1 Wait input by WAIT pin
enabled
Reserved
Only 0 should be written to this bit.
Reserved
Only 1 should be written to these bits.
External Address Enable
0 ^{Addresses H'010000 to H'03FFFF*2:}
• H8S/2319, H8S/2319C, H8S/2315, and H8S/2314: On-chip ROM
• H8S/2318: On-chip ROM
• H8S/2317, H8S/2317S: On-chip ROM at addresses H'010000 to H'01FFFF
and reserved area^*1 at addresses H'020000 to H'03FFFF
• H8S/2316S: Reserved area^*1
1 Addresses H'010000 to H'03FFFF^*2:
• Expanded mode: External addresses
• Single-chip mode: Reserved area^*1
Notes: 1. Do not access a reserved area.
2. H'010000 to H'03FFFF in the H8S/2318, H'010000 to H'05FFFF
in the H8S/2315 and H8S/2314, and H'010000 to H'07FFFF in the
H8S/2319 and H8S/2319C.
BREQO Pin Enable
0 BREQO output disabled
1 BREQO output enabled
Bus Release Enable
0 External bus release disabled
1 External bus release enabled
Rev.7.00 Feb. 14, 2007 page 989 of 1108
REJ09B0089-0700