D12320VF25V Datasheet, PDF (570/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 A/D Converter (8 Analog Input Channel Version)
14.2.2 A/D Control/Status Register (ADCSR)
Bit
:
Initial value :
R/W
:
7
ADF
0
R/(W)^*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows
the status of the operation.
ADCSR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF
0
1
Description
[Clearing conditions]
• When 0 is written to the ADF flag after reading ADF = 1
• When the DTC is activated by an ADI interrupt and ADDR is read
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
(Initial value)
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE
0
1
Description
A/D conversion end interrupt (ADI) request disabled
A/D conversion end interrupt (ADI) request enabled
(Initial value)
Rev.7.00 Feb. 14, 2007 page 536 of 1108
REJ09B0089-0700