D12320VF25V Datasheet, PDF (474/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Serial Communication Interface (SCI)
Bit 3
STOP
0
1
Description
1 stop bit: In transmission, a single 1-bit (stop bit) is added to the end of a transmit
character before it is sent.
(Initial value)
2 stop bits: In transmission, two 1-bits (stop bits) are added to the end of a transmit
character before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 12.3.3, Multiprocessor
Communication Function.
Bit 2
MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 12.2.8, Bit Rate Register (BRR).
Bit 1
CKS1
0
1
Bit 0
CKS0
0
1
0
1
Description
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
(Initial value)
Rev.7.00 Feb. 14, 2007 page 440 of 1108
REJ09B0089-0700