D12320VF25V Datasheet, PDF (322/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
1
—
INTM1 INTM0 NMIEG LWROD —
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
0
RAME
1
R/W
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in
modes 4 to 6.
Bit 2
LWROD
0
1
Description
PF3 is designated as LWR output pin
(Initial value)
PF3 is designated as I/O port, and does not function as LWR output pin
Bus Control Register L (BCRL)
Bit
:
7
6
5
4
3
2
1
0
BRLE BREQOE EAE
—
—
—
— WAITE
Initial value :
0
0
1
1
1
1
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
(Initial value)
External bus release enabled
Rev.7.00 Feb. 14, 2007 page 288 of 1108
REJ09B0089-0700