D12320VF25V Datasheet, PDF (1027/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

ISR—IRQ Status Register
Appendix B Internal I/O Registers
H'FF2F
Interrupt Controller
Bit
:
Initial value :
Read/Write :
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests
Bit n
IRQnF
Description
0
[Clearing conditions]
(Initial value)
• When 0 is written to IRQnF after reading IRQnF = 1
• When interrupt exception handling is executed while low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed while falling, rising, or both-
edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt and the DISEL bit in the DTC's
MRB register is 0
1
[Setting conditions]
• When IRQn input goes low while low-level detection is set (IRQnSCB =
IRQnSCA = 0)
• When a falling edge occurs in IRQn input while falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input while rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge detection is
set (IRQnSCB = IRQnSCA = 1)
Note: * Can only be written with 0 for flag clearing.
(n = 7 to 0)
Rev.7.00 Feb. 14, 2007 page 993 of 1108
REJ09B0089-0700