D12320VF25V Datasheet, PDF (20/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.5 Usage Notes ...................................................................................................................... 134
5.5.1 Contention between Interrupt Generation and Disabling..................................... 134
5.5.2 Instructions that Disable Interrupts ...................................................................... 135
5.5.3 Times when Interrupts are Disabled .................................................................... 135
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 135
5.6 DTC Activation by Interrupt............................................................................................. 136
5.6.1 Overview.............................................................................................................. 136
5.6.2 Block Diagram ..................................................................................................... 136
5.6.3 Operation ............................................................................................................. 137
Section 6 Bus Controller....................................................................................139
6.1 Overview........................................................................................................................... 139
6.1.1 Features................................................................................................................ 139
6.1.2 Block Diagram ..................................................................................................... 140
6.1.3 Pin Configuration................................................................................................. 141
6.1.4 Register Configuration......................................................................................... 142
6.2 Register Descriptions ........................................................................................................ 143
6.2.1 Bus Width Control Register (ABWCR)............................................................... 143
6.2.2 Access State Control Register (ASTCR) ............................................................. 144
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 145
6.2.4 Bus Control Register H (BCRH) ......................................................................... 148
6.2.5 Bus Control Register L (BCRL) .......................................................................... 150
6.3 Overview of Bus Control .................................................................................................. 152
6.3.1 Area Partitioning.................................................................................................. 152
6.3.2 Bus Specifications................................................................................................ 153
6.3.3 Memory Interfaces ............................................................................................... 154
6.3.4 Advanced Mode ................................................................................................... 155
6.3.5 Chip Select Signals .............................................................................................. 156
6.4 Basic Bus Interface ........................................................................................................... 157
6.4.1 Overview.............................................................................................................. 157
6.4.2 Data Size and Data Alignment............................................................................. 157
6.4.3 Valid Strobes........................................................................................................ 159
6.4.4 Basic Timing........................................................................................................ 160
6.4.5 Wait Control ........................................................................................................ 168
6.5 Burst ROM Interface......................................................................................................... 170
6.5.1 Overview.............................................................................................................. 170
6.5.2 Basic Timing........................................................................................................ 170
6.5.3 Wait Control ........................................................................................................ 172
6.6 Idle Cycle .......................................................................................................................... 173
6.6.1 Operation ............................................................................................................. 173
Rev.7.00 Feb. 14, 2007 page xviii of xxxii
REJ09B0089-0700