D12320VF25V Datasheet, PDF (626/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2318 F-ZTAT,
H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or H8S/2314 F-ZTAT chip measures the low period of
the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI
transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip
calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset),
and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s
system clock frequency, there will be a discrepancy between the bit rates of the host and the chip.
To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps.
Table 17.10 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more bits)
Figure 17.11 Automatic SCI Bit Rate Adjustment
Table 17.10 System Clock Frequencies for Which Automatic Adjustment of H8S/2318
F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or H8S/2314 F-ZTAT Bit
Rate Is Possible
Host Bit Rate
19,200 bps
9,600 bps
System Clock Frequency for Which Automatic Adjustment
of H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or
H8S/2314 F-ZTAT Bit Rate Is Possible
16 to 25 MHz
8 to 25 MHz
Rev.7.00 Feb. 14, 2007 page 592 of 1108
REJ09B0089-0700