D12320VF25V Datasheet, PDF (207/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.6 Idle Cycle
6.6.1 Operation
When the chip accesses external space, it can insert a 1-state idle cycle (T_I) between bus cycles in
the following two cases: (1) when read accesses in different areas occur consecutively, and (2)
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, with a long output floating time, and high-
speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is
enabled in advanced mode.
Figure 6.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
φ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Data
Long output _collision
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
Figure 6.16 Example of Idle Cycle Operation (1)
Rev.7.00 Feb. 14, 2007 page 173 of 1108
REJ09B0089-0700