D12320VF25V Datasheet, PDF (423/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T₂ state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes
precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.57 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
TCNT
TCFV flag
H'FFFF
Prohibited
TCNT write data
M
Figure 9.57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O
pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O
pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input,
compare match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Rev.7.00 Feb. 14, 2007 page 389 of 1108
REJ09B0089-0700