D12320VF25V Datasheet, PDF(582/1146 Page) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

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D12320VF25V Datasheet, PDF (582/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

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Section 14 A/D Converter (8 Analog Input Channel Version)

14.6 Usage Notes

The following points should be noted when using the A/D converter.

Setting Range of Analog Power Supply and Other Pins

1. Analog input voltage range

The voltage applied to analog input pins ANn during A/D conversion should be in the range

AVSS â¤ ANn â¤ Vref.

2. Relation between AVCC, AVSS and VCC, VSS

As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter

is not used, the AVCC and AVSS pins must not be left open.

3. Vref input range

The analog reference voltage input at the Vref pin should be set in the range Vref â¤ AVCC. The

Vref pin should be set as Vref = VCC when the A/D converter is not used. Do not leave the Vref

pin open.

If conditions 1, 2, and 3 above are not met, the reliability of the device may be adversely affected.

Notes on Board Design: In board design, digital circuitry and analog circuitry should be as

mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit

signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so

may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D

conversion values.

Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog

reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS).

Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)

on the board.

Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an

abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog

reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure

14.7.

Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0

to AN7 must be connected to AVSS.

If a filter capacitor is connected as shown in figure 14.7, the input currents at the analog input pins

(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed

Rev.7.00 Feb. 14, 2007 page 548 of 1108

REJ09B0089-0700

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