D12320VF25V Datasheet, PDF (188/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ABWn
0
ASTCR
ASTn
0
1
1
0
1
WCRH, WCRL
Wn1
—
0
1
—
0
1
Wn0
—
0
1
0
1
—
0
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width
Program Wait
Access States States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
6.3.3 Memory Interfaces
The chip’s memory interfaces comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; and a burst ROM interface that allows direct connection of burst ROM.
The interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.
Rev.7.00 Feb. 14, 2007 page 154 of 1108
REJ09B0089-0700