D12320VF25V Datasheet, PDF (538/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Smart Card Interface
Bit 2
SINV
0
1
Description
TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
(Initial value)
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface
function.
Bit 0
SMIF
0
1
Description
Smart card interface function is disabled
Smart card interface function is enabled
(Initial value)
13.2.2 Serial Status Register (SSR)
Bit
:
Initial value :
R/W
:
7
TDRE
1
R/(W)^*
6
RDRF
0
R/(W)^*
5
ORER
0
R/(W)^*
4
ERS
0
R/(W)^*
3
PER
0
R/(W)^*
2
TEND
1
R
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
1
MPB
0
R
0
MPBT
0
R/W
Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
smart card interface mode.
Rev.7.00 Feb. 14, 2007 page 504 of 1108
REJ09B0089-0700