D12320VF25V Datasheet, PDF (209/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.18.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
Figure 6.18 Relationship between Chip Select (CS) and Read (RD)
Rev.7.00 Feb. 14, 2007 page 175 of 1108
REJ09B0089-0700