D12320VF25V Datasheet, PDF (112/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
3.3.3 Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)
This is a flash memory boot mode. See section 17, ROM, for details.
Except for the fact that flash memory programming and erasing can be performed, operation in
this mode is the same as in advanced single chip mode.
3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, ports A, B, and C function as an address bus, ports D and E functions as a data
bus, and part of port F carries bus control signals.
Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output
addresse by setting the corresponding data direction register (DDR) bits and A23E to A20E in
PFCR1 to 1.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if
8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, ports A, B, and C function as an address bus, port D functions as a data bus, and
part of port F carries bus control signals.
Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output
addresses by setting the corresponding data direction register (DDR) bits and A23E to A20E in
PFCR1 to 1.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at
least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16
bits and port E becomes a data bus.
Rev.7.00 Feb. 14, 2007 page 78 of 1108
REJ09B0089-0700