D12320VF25V Datasheet, PDF (185/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access.
Bit 6
BREQOE
0
1
Description
BREQO output disabled. BREQO pin can be used as I/O port
BREQO output enabled
(Initial value)
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*² are
to be internal addresses or external addresses.
Description
Bit 5
EAE
0
1
H8S/2319, H8S/2319C,
H8S/2318, H8S/2315,
H8S/2314
H8S/2317(S)^*3
H8S/2316S
On-chip ROM
Addresses H'010000 to H'01FFFF are Reserved area^*1
on-chip ROM and addresses H'020000
to H'03FFFF are reserved area^*1
Addresses H'010000 to H'03FFFF^*2 are external addresses in external expanded mode
or reserved area^*1 in single-chip mode
(Initial value)
Notes: 1. Do not access a reserved area.
2. H'010000 to H'03FFFF in the H8S/2318.
H'010000 to H'05FFFF in the H8S/2315 and H8S/2314.
H'010000 to H'07FFFF in the H8S/2319 and H8S/2319C.
3. H8S/2317S in mask ROM version.
Bits 4 to 2—Reserved: Only 1 should be written to these bits.
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
Wait input by WAIT pin enabled
(Initial value)
Rev.7.00 Feb. 14, 2007 page 151 of 1108
REJ09B0089-0700