D12320VF25V Datasheet, PDF (222/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER are not performed.
When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit.
Bit 7
CHNE
0
1
Description
End of DTC data transfer (activation waiting state)
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
0
1
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bit 5—DTC Chain Transfer Select (CHNS): Specifies the chain transfer condition when CHNE
is 1.
Bit 7
CHNE
0
1
Bit 5
CHNS
–
0
1
Description
No chain transfer (DTC data transfer end, activation waiting state entered)
DTC chain transfer
Chain transfer only when transfer counter = 0
Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the chip and should always
be written with 0.
Rev.7.00 Feb. 14, 2007 page 188 of 1108
REJ09B0089-0700