D12320VF25V Datasheet, PDF (836/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Power-Down Modes
Table 19.1 Operating Modes
Operating Transition Clearing
Mode
Condition Condition Oscillator
CPU
Registers
Modules
Registers I/O Ports
High speed Control
mode
register
Control
register
Functions High Function
speed
High Function High speed
speed
Medium- Control
speed mode register
Control
register
Functions Medium Function
speed
High/ Function
medium
speed ^*1
High speed
Sleep mode Instruction Interrupt
Functions Halted Retained
High Function High speed
speed
Module stop Control
mode
register
Control
register
Functions
High/ Function
medium
speed
Halted Retained/ Retained
reset ^*2
Software
standby
mode
Instruction External
interrupt
Halted
Halted Retained
Halted Retained/ Retained
reset ^*2
Hardware Pin
Pin
Halted
Halted Undefined Halted Reset
High
standby
impedance
mode
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting
modules on the high-speed clock.
2. Some SCI registers and the A/D converter are reset, and other on-chip supporting
modules retain their states.
19.1.1 Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 19.2
summarizes these registers.
Table 19.2 Power-Down Mode Registers
Name
Abbreviation
Standby control register
SBYCR
System clock control register
SCKCR
Module stop control register H MSTPCRH
Module stop control register L MSTPCRL
Note: * Lower 16 bits of the address.
R/W
R/W
R/W
R/W
R/W
Initial Value
H'08
H'00
H'3F
H'FF
Address^*
H'FF38
H'FF3A
H'FF3C
H'FF3D
Rev.7.00 Feb. 14, 2007 page 802 of 1108
REJ09B0089-0700