D12320VF25V Datasheet, PDF (742/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
Bits 15 to 0—Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting
value must be calculated as the following methods.
1. The operating frequency which is shown in MHz units must be rounded in a number to three
decimal places and be shown in a number of two decimal places.
2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ
parameter (general register ER0). For example, when the operating frequency of the CPU is
25.000 MHz, the value is as follows.
• The number to three decimal places of 25.000 is rounded and the value is thus 25.00.
• The formula that 25.00 × 100 = 2500 is converted to the binary digit and
b'0000,1001,1100,0100 (H'09C4) is set to ER0.
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This is the return value indicating the initialization result.
Bit
:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FQ
SF
Initial value : —
—
—
—
—
—
—
—
R/W
:—
—
—
—
—
—
R/W
R/W
Bits 7 to 2—Reserved: Return 0.
Bit 1—Frequency Error Detect (FQ): Returns the check result whether the specified operating
frequency of the CPU is in the range of the supported operating frequency.
Bit 1
FQ
0
1
Description
Setting of operating frequency is normal
Setting of operating frequency is abnormal
Bit 0—Success/Fail (SF): Indicates whether initialization is completed normally.
Bit 0
SF
0
1
Description
Initialization is ended normally (no error)
Initialization is ended abnormally (error occurs)
Rev.7.00 Feb. 14, 2007 page 708 of 1108
REJ09B0089-0700