D12320VF25V Datasheet, PDF (444/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 8-Bit Timers
10.6.3 Contention between TCOR Write and Compare Match
During the T₂ state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs.
Figure 10.12 shows this operation.
TCOR write cycle by CPU
T₁
T₂
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare match signal
TCOR write data
Inhibited
Figure 10.12 Contention between TCOR Write and Compare Match
Rev.7.00 Feb. 14, 2007 page 410 of 1108
REJ09B0089-0700