D12320VF25V Datasheet, PDF (755/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
This LSI
Host
Boot
programming
tool and program
data
Control command, program data
Reply response
Control command,
analysis execution
software (on-chip)
RxD1
On-chip SCI1
TxD1
Flash
memory
On-chip RAM
Figure 17.65 System Configuration in Boot Mode
SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of
asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates
the bit rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation described
above must be executed. The bit rate between the host and this LSI is not matched by the bit rate
of transmission by the host and system clock frequency of this LSI. To operate the SCI normally,
the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the
bit rate of this LSI is shown in table 17.53. Boot mode must be initiated in the range of this system
clock.
Start
bit
D0 D1 D2 D3 D4 D5 D6
Stop bit
D7
Measure low period (9 bits) (data is H'00)
High period of
at least 1 bit
Figure 17.66 Automatic Adjustment Operation of SCI Bit Rate
Rev.7.00 Feb. 14, 2007 page 721 of 1108
REJ09B0089-0700