D12320VF25V Datasheet, PDF (232/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Data Transfer Controller
Source flag clearance
Clear
DTCER
Select
Clear
control
Clear request
On-chip
supporting
module
IRQ interrupt
DTVECR
Interrupt
request
DTC
Interrupt controller
Interrupt mask
CPU
Figure 7.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
7.3.3 DTC Vector Table
Figure 7.4 shows the correspondence between DTC vector addresses and register information.
Table 7.5 shows the correspondence between activation, vector addresses, and DTCER bits. When
the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0]
<< 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector
address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register information should be an integral multiple of four.
The configuration of the vector address is a 2-byte unit. These two bytes specify the lower bits of
the address in the on-chip RAM.
Rev.7.00 Feb. 14, 2007 page 198 of 1108
REJ09B0089-0700