D12320VF25V Datasheet, PDF (420/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T₂ state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 9.54 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T₁
T₂
TGR address
M
TGR
M
Figure 9.54 Contention between TGR Write and Input Capture
Rev.7.00 Feb. 14, 2007 page 386 of 1108
REJ09B0089-0700