D12320VF25V Datasheet, PDF (413/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.46 shows the timing
for status flag clearing by the CPU, and figure 9.47 shows the timing for status flag clearing by the
DTC.
TSR write cycle
T₁
T₂
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 9.46 Timing for Status Flag Clearing by CPU
DTC
read cycle
T₁
T₂
DTC
write cycle
T₁
T₂
φ
Address
Status flag
Source address
Destination
address
Interrupt
request
signal
Figure 9.47 Timing for Status Flag Clearing by DTC Activation
Rev.7.00 Feb. 14, 2007 page 379 of 1108
REJ09B0089-0700