D12320VF25V Datasheet, PDF (356/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
3
0000
TGR3D Output disabled
(Initial value)
1
10
is output _{Initial output is 0 0 output at compare match}
compare
register^*2
output
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1000
1
1×
1××
TGR3D Capture input Input capture at rising edge
is input source is
capture TIOCD3 pin
register^*2
Input capture at falling edge
Input capture at both edges
Capture input Input capture at TCNT4
source is channel count-up/count-down^*1
4/count clock
×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Feb. 14, 2007 page 322 of 1108
REJ09B0089-0700