D12320VF25V Datasheet, PDF (175/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the bus controller.
Table 6.1 Bus Controller Pins
Name
Address strobe
Symbol
AS
I/O
Output
Read
RD
Output
High write
HWR
Output
Low write
LWR
Output
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request
acknowledge
Bus request output
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
WAIT
BREQ
BACK
BREQO
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Function
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is
to be written, and upper half (D15 to D8) of data
bus is enabled.
Strobe signal indicating that external space is
to be written, and lower half (D7 to D0) of data
bus is enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
Strobe signal indicating that area 3 is selected.
Strobe signal indicating that area 4 is selected.
Strobe signal indicating that area 5 is selected.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
Wait request signal when accessing external 3-
state access space.
Request signal that releases bus to external
device.
Acknowledge signal indicating that bus has
been released.
External bus request signal used when internal
bus master accesses external space when
external bus is released.
Rev.7.00 Feb. 14, 2007 page 141 of 1108
REJ09B0089-0700