D12320VF25V Datasheet, PDF (680/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.14.4 Erase Block Register 2 (EBR2)
Bit
:
7
6
5
4
3
2
1
0
EBR2
EB15 EB14 EB13 EB12 EB11 EB10 EB9
EB8
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the
SWE1 bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be
erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting
more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 17.28.
Table 17.28 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kbytes)
EB1 (4 kbytes)
EB2 (4 kbytes)
EB3 (4 kbytes)
EB4 (4 kbytes)
EB5 (4 kbytes)
EB6 (4 kbytes)
EB7 (4 kbytes)
EB8 (32 kbytes)
EB9 (64 kbytes)
EB10 (64 kbytes)
EB11 (64 kbytes)
EB12 (64 kbytes)
EB13 (64 kbytes)
EB14 (64 kbytes)
EB15 (64 kbytes)
Address
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
H'008000 to H'00FFFF
H'010000 to H'01FFFF
H'020000 to H'02FFFF
H'030000 to H'03FFFF
H'040000 to H'04FFFF
H'050000 to H'05FFFF
H'060000 to H'06FFFF
H'070000 to H'07FFFF
Rev.7.00 Feb. 14, 2007 page 646 of 1108
REJ09B0089-0700