D12320VF25V Datasheet, PDF (173/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Section 6 Bus Controller
6.1 Overview
The chip has a built-in bus controller (BSC) that manages the external address space divided into
eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
6.1.1 Features
The features of the bus controller are listed below.
• Manages external address space in area units
⎯ In advanced mode, manages the external space as 8 areas of 2 Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interfaces can be set
• Basic bus interface
⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
• Other features
⎯ External bus release function
Rev.7.00 Feb. 14, 2007 page 139 of 1108
REJ09B0089-0700