D12320VF25V Datasheet, PDF (78/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
2.6.3 Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3
is defined below.
Operation Notation
Rd
General register (destination)^*
Rs
General register (source)^*
Rn
General register^*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
¬
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev.7.00 Feb. 14, 2007 page 44 of 1108
REJ09B0089-0700