D12320VF25V Datasheet, PDF (138/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Exception Handling
4.3 Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4.3 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4.3 Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
0
2
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
CCR
EXR
I
UI
I2 to I0
T
Trace exception handling cannot be used.
1
—
—
0
Rev.7.00 Feb. 14, 2007 page 104 of 1108
REJ09B0089-0700