D12320VF25V Datasheet, PDF (845/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Power-Down Modes
19.6 Software Standby Mode
19.6.1 Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state or retain the output
state can be specified by the OPE bit in SBYCR. See appendix D, Pin States, for details.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
19.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7^*), or
by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an NMI or IRQ0 to IRQ7* interrupt request signal is input,
clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable
clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception
handling is started.
When clearing software standby mode with an IRQ0 to IRQ7* interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7* is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Note: * Setting the IRQ37S bit to 1 enables IRQ3 to IRQ7 to be used as software standby mode
clearing sources.
Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to
hardware standby mode.
Rev.7.00 Feb. 14, 2007 page 811 of 1108
REJ09B0089-0700