D12320VF25V Datasheet, PDF (752/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
17.23.4 RAM Emulation Register (RAMER)
Bit
:
7
6
5
4
—
—
—
—
Initial value :
0
0
0
0
R/W
:—
—
—
—
3
RAMS
0
R/W
2
RAM2
0
R/W
1
RAM1
0
R/W
0
RAM0
0
R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 17.51. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Bit 3
RAMS
0
1
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
(Initial value)
Rev.7.00 Feb. 14, 2007 page 718 of 1108
REJ09B0089-0700