D12320VF25V Datasheet, PDF (1058/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SCR1—Serial Control Register 1
H'FF82
SCI1
Bit
:
7
TIE
Initial value :
0
Read/Write :
R/W
6
5
RIE
TE
0
0
R/W
R/W
4
3
2
1
0
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Clock Enable
0 0 Asynchronous Internal clock/SCK pin functions
mode
as I/O port
Synchronous Internal clock/SCK pin functions
mode
as serial clock output
1 Asynchronous Internal clock/SCK pin functions
mode
as clock output^*1
Synchronous Internal clock/SCK pin functions
mode
as serial clock output
1 0 Asynchronous External clock/SCK pin functions
mode
as clock input^*2
Synchronous External clock/SCK pin functions
mode
as serial clock input
1 Asynchronous External clock/SCK pin functions
mode
as clock input^*2
Synchronous External clock/SCK pin functions
mode
as serial clock input
Notes: 1. Outputs a clock of the same frequency as the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate
Transmit End Interrupt Enable
0 Transmit-end interrupt (TEI) request disabled*
1 Transmit-end interrupt (TEI) request enabled*
Note: * TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
Multiprocessor Interrupt Enable
0 Multiprocessor interrupts disabled
[Clearing conditions]
· When the MPIE bit is cleared to 0
· When data with MPB = 1 is received
1 Multiprocessor interrupts enabled*
Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit
set to 1 is received
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not
performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1,
the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when
the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
Receive Enable
0 Reception disabled^*1
1 Reception enabled^*2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock
input is detected in synchronous mode.
SMR setting must be performed to decide the receive format before setting the RE bit to 1.
Transmit Enable
0 Transmission disabled^*1
1 Transmission enabled^*2
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmit format before setting the TE bit to 1.
Receive Interrupt Enable
0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*
1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or
ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
Transmit Interrupt Enable
0 Transmit-data-empty interrupt (TXI) request disabled*
1 Transmit-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by reading 1 from the
TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
Rev.7.00 Feb. 14, 2007 page 1024 of 1108
REJ09B0089-0700