D12320VF25V Datasheet, PDF (339/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.1.2 Block Diagram
Figure 9.1 shows a block diagram of the TPU.
Section 9 16-Bit Timer Pulse Unit (TPU)
Input/output pins
Channel 3: TIOCA3
TIOCB3
TIOCC3
TIOCD3
Channel 4: TIOCA4
TIOCB4
Channel 5: TIOCA5
TIOCB5
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0: TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1: TIOCA1
TIOCB1
Channel 2: TIOCA2
TIOCB2
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start request signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Figure 9.1 Block Diagram of TPU
Rev.7.00 Feb. 14, 2007 page 305 of 1108
REJ09B0089-0700