D12320VF25V Datasheet, PDF (195/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D₁₅ to D₈) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
φ
Address bus
CSn
AS
RD
Read D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
High
Valid
D₇ to D₀
High impedance
Note: n = 0 to 7
Figure 6.7 Bus Timing for 8-Bit 3-State Access Space
Rev.7.00 Feb. 14, 2007 page 161 of 1108
REJ09B0089-0700