D12320VF25V Datasheet, PDF (765/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
[15] After programming finishes, clear FKEY and specify software protection.
If this LSI is restarted by a power-on reset immediately after user MAT programming has
finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 μs.
Erasing Procedure in User Program Mode: The procedures for download, initialization, and
erasing are shown in figure 17.71.
Start erasing procedure
program
Select on-chip program
to be downloaded and set
download destination
(a)
by FTDAR
Set FKEY to H'A5
Set SCO to 1 and
execute download
Clear FKEY to 0
DPFR = 0?
Yes
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR setting+32
FPFR=0 ?
No
Yes _{Initialization error processing}
1
1
Disable interrupts and
bus master operation
other than CPU
Set FKEY to H'5A
Set FEBS parameter
(b)
Erasing
JSR FTDAR setting+16 (c)
FPFR=0 ?
(d)
No
Yes _{Clear FKEY and erasing}
error processing
No
Required block
erasing is
completed?
(e)
Yes
Clear FKEY to 0
(f)
End erasing
procedure program
Figure 17.71 Erasing Procedure
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-
chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 17.29.3, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in
figure 17.69.
Rev.7.00 Feb. 14, 2007 page 731 of 1108
REJ09B0089-0700