D12320VF25V Datasheet, PDF (479/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Serial Communication Interface (SCI)
12.2.7 Serial Status Register (SSR)
Bit
:
Initial value :
R/W
:
7
TDRE
1
R/(W)^*
6
RDRF
0
R/(W)^*
5
ORER
0
R/(W)^*
4
FER
0
R/(W)^*
3
PER
0
R/(W)^*
2
TEND
1
R
Note: * Only 0 can be written, to clear the flag.
1
MPB
0
R
0
MPBT
0
R/W
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and in standby mode or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
0
1
Description
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
(Initial value)
• When data is transferred from TDR to TSR and data can be written to TDR
Rev.7.00 Feb. 14, 2007 page 445 of 1108
REJ09B0089-0700