D12320VF25V Datasheet, PDF (842/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Power-Down Modes
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made
to software standby mode. When software standby mode is cleared by an external interrupt,
medium-speed mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 19.1 shows the timing for transition to and clearance of medium-speed mode.
φ,
supporting module
clock
Bus master clock
Medium-speed mode
Internal address bus SCKCR
SCKCR
Internal write signal
Figure 19.1 Medium-Speed Mode Transition and Clearance Timing
19.4 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program
execution state via the exception handling state. Sleep mode is not cleared if interrupts are
disabled, or if interrupts other than NMI are masked by the CPU.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev.7.00 Feb. 14, 2007 page 808 of 1108
REJ09B0089-0700