D12320VF25V Datasheet, PDF (329/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
Port G Data Register (PGDR)
Bit
:7
6
5
4
—
—
— PG4DR
Initial value : Undefined Undefined Undefined 0
R/W
:—
—
—
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to
PG0).
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port G Register (PORTG)
Bit
:7
6
5
4
—
—
—
PG4
Initial value : Undefined Undefined Undefined —^*
R/W
:—
—
—
R
Note: * Determined by state of pins PG4 to PG0.
3
PG3
—^*
R
2
PG2
—^*
R
1
PG1
—^*
R
0
PG0
—^*
R
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG4 to PG0) must always be performed on PGDR.
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.
Rev.7.00 Feb. 14, 2007 page 295 of 1108
REJ09B0089-0700